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2013 IEEE High Performance Extreme Computing Conference (HPEC ‘13) Seventeenth Annual HPEC Conference 10 - 12 September 2013 Westin Hotel, Waltham, MA USA
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Real-Time Traffic Sign Detection Using SURF Features on FPGA Jin Zhao, WPI; Sichao Zhu, WPI; Xinming Huang, Worcester Polytechnic Institute Abstract: Drivers' failure to observe traffic signs, especially the stop signs, has led to many serious traffic accidents. Video-based traffic sign detection is an important component of driver-assistance systems. In earlier systems, simple color and shape-based detection methods have been broadly applied. Recently, feature-based traffic sign detection algorithms are proposed to obtain more accurate results, especially when combined with the previous two. The Speeded Up Robust Features (SURF) algorithm is an outstanding feature detector and descriptor with rotation and illumination invariance. Unfortunately, due to its computational complexity, the application of SURF algorithm remains limited in real-time systems. In this paper, we present a real-time SURF-based traffic sign detection system by exploiting parallelism and rich resources in FPGAs. The proposed hardware design is able to accurately process video streams of 800 x 600 resolution at 25 frame per second. Vendor Agnostic, High Performance, Double Precision Floating Point Division for FPGAs Miriam Leeser, Northeastern University; Xin Fang, NEU ECE Department Abstract: Double precision Floating Point (FP) arithmetic operations are widely used in many applications such as image and signal processing and scientific computing. Field Programmable Gate Arrays (FPGAs) are a popular platform for accelerating such applications due to their relative high performance, flexibility and low power consumption compared to general purpose processors and GPUs.  Increasingly scientists are interested in double precision FP operations implemented on FPGAs.  FP division and square root are much more difficult to implement than addition and multiplication.  In this paper we focus on  a fast divider design for double precision floating point that makes efficient use of FPGA resources including embedded multipliers.  The design is table based; we compare it to iterative and digit recurrence implementations.  Our division implementation targets performance with balanced latency and high clock frequency.  Our design has been implemented on both Xilinx and Altera FPGAs. The table based double precision floating point divider provides a good tradeoff between area and performance and produces good results when targeting both Xilinx and Altera FPGAs. FPGA-based Hyperspectral Covariance Coprocessor for Size, Weight, and Power Constrained Platforms David Kusinsky, MIT Lincoln Laboratory; Miriam Leeser, Northeastern University Abstract: Size, weight, and power (SWaP) are important factors in the design of any remote sensing platform.  These remote sensing platforms, such as Unmanned Air Vehicles (UAVs) and microsatellites, are becoming increasingly small.  This creates a need for remote sensing and image processing hardware that consumes less area, weight, and power, while delivering processing performance.  It is also advantageous to utilize the same hardware for multiple platform tasks.  The purpose of this research is to design and characterize an FPGA-based hardware coprocessor that parallelizes the calculation of covariance, a time-consuming step common in hyperspectral image processing.  Our design is compared to a CPU-based implementation and shown to have an overall SWaP advantage.  We evaluate our coprocessor using a metric that is useful in the consideration of future SWaP-constrained remote sensing platforms: floating point operations per Watt-kg (FLOPs/W-kg).  Additional hardware capacity exists in our design to implement other remote sensing platform tasks.