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2013 IEEE High Performance Extreme Computing Conference (HPEC ‘13) Seventeenth Annual HPEC Conference 10 - 12 September 2013 Westin Hotel, Waltham, MA USA
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Instructor: Ian Linault, Managing Director of nCore TI has created a chip family that contains both high-end ARM cores and TI’s DSP cores. They also created a new tool flow that makes the DSP cores available using OpenMP. The result is an accelerated ARM system looking to programs very much like an Intel system accelerated by Intel’s Phi chips. The TI system offers very different power/performance characteristics. During the HPEC conference, TI’s Director of Silicon Development, Sanjive Agarwala, will talk about Keystone II’s power characteristics. Our tutorial will focus beyond Sanjive’s talk on programming the TI Keystone II. In the tutorial room we will use a modest configuration of the “Brown Dwarf” supercomputer. We will talk about the tools you need and where to obtain them. We assume attendees are somewhat familiar with OpenMP. Thus we will focus on the differences introduced by the recent “accelerator model” enhancements to OpenMP. We will look at a Keystone II implementation of the HPEC Challenge TDFIR benchmark. We use TDFIR because it is simple and familiar to the HPEC community. The HPEC benchmark includes data and a test harness that verifies our results are correct. We also have implementations on many platforms that we can reference. Putting attendees in front of Brown Dwarf terminals is not practical in a half-day session but the system will remain at HPEC for the full conference.  We can make an internet login available to students after the tutorial if there is interest. We will propose a lab exercise. Brown Dwarf uses RapidIO as its multichip interconnect and Open MPI to communicate over RapidIO. The tutorial will briefly discuss Open MPI on Keystone II. Brown Dwarf (and CSPI’s boards) use nCore’s Keystone II Linux. The OpenMP tool flow does not run on those ARM cores. It is a cross compilation from an x86 host (Windows or Linux). An OpenCL tool flow is also available.  We will only briefly discuss it. Programmers are also free to use TI’s Eclipse-based programming environment called Code Composer Studio (CCS). We will spend a little time on CCS but the nCore flavor of the TI tools makes CCS optional. The tutorial is supported by nCore, CSPi, and TI.
Tutorial:  Using OpenMP to accelerate an ARM system using DSP cores