30th Annual
IEEE High Performance Extreme Computing Virtual Conference
14 - 18 September 2026

All times are EDT (UTC/GMT -04 hours)
Speaker/Presenting Author in Italics

Thursday, September 17

4-1 + 4-K: Advanced Multicore Software Technologies; Automated Design Tools + Keynote (10:30 AM-12:30 PM)

Session Chair/Session Host: J.Ghanem & A. Reuther

Adaptive Row Selection Meets Asynchrony in Randomized Kaczmarz
Evan Coleman (Univ. of Mary Washington)

Randomized Kaczmarz is a natural fit for large sparse least-squares and tomographic reconstruction, and adaptive row selection can reduce iteration counts. However, deploying adaptive selection on a shared-memory machine means sampling from a residual that lock-free workers are concurrently modifying, often using stale data. We present the first systematic study of this regime: residual-weighted and greedy Kaczmarz under asynchronous execution, measured across 339 runs on a 96-core node with realized (not injected) delays. Four findings carry directly to practice. (i) Stability is governed by a boundary ℓ∗(T) between sampling aggressiveness and thread count; below it, more aggressive sampling is strictly better, so one should tune to just inside the cliff. (ii) Threshold-greedy selection (the standard accelerated rule) is unstable at high thread counts, diverging almost immediately. (iii) Under-relaxation buys back the cliff at a predictable cost, giving a usable safety knob. (iv) Consistentsnapshot reads admit a rare, scheduling-dependent divergence that live (inconsistent) reads never exhibited; live reads also cost less per step, making them the right default. We validate the implementation against published sequential results and outline the distributed two-level sampler these measurements motivate. 

Increasing Metadata Parallelism through Hybrid Inode Ownership
Matthew Curtis-Maury, Jian Hu, Bulli Venkata Rajesh Vipperla, Sushrut Bhowmik, Grey Files, Bryan Prosser (NetApp)

Metadata-intensive workloads such as electronic design automation (EDA) and software builds generate substantial inode activity, making inode ownership a significant source of serialization in multicore storage systems. In partition-based file systems, operations requiring exclusive inode access often experience excessive serialization, limiting available metadata parallelism. This paper presents Hybrid Inode Ownership (HIO), a synchronization mechanism that decouples inode ownership from the underlying data partitions. HIO combines shared ownership, promotion to exclusive access, and suspension-based conflict resolution, allowing metadata operations to execute within finer-grained partitions while preserving existing execution models. HIO has been applied to a broad range of operations. Evaluation on production storage platforms shows that HIO more than doubles peak throughput for single-volume EDA and software-build workloads. HIO also improves SetAttr throughput by up to 87% and significantly improves Unlink performance. Mechanism analysis shows that HIO moves ownership-sensitive operations out of coarse-grained data partitions, exposing substantial additional filesystem parallelism. In contrast, workloads with little inode-ownership contention or that already have sufficient parallelism despite coarse inode synchronization exhibit negligible overhead. These results demonstrate that inode-scoped ownership provides an effective and incremental approach for recovering metadata parallelism in large production file systems.

Single-Source Scalar and SIMD Particle Kernels with Compile-Time Memory Abstractions
Julian Deller-Yee, Manish Kumar Mishra, and Hans Joachim Bungartz (Tech. Univ. Munich)

High-performance particle simulation frameworks face a fundamental tension: extracting maximum CPU performance requires hardware-aware data layouts, such as SoA and AoSoA, and explicit SIMD vectorization, but exposing these details to user-facing code degrades modularity and extensibility. Traditional runtime abstractions can obscure hot paths from the compiler, leading to suboptimal machine code. This paper demonstrates how modern C++ compile-time techniques can reconcile modularity and extensibility with optimized execution. Using APRIL, a statically composed particle simulation framework, as a testbed, we present an abstraction for particle interaction kernels that combines field-restricted accessors, layout-specific binding, and SIMD types with scalar-like semantics. Users express each interaction once through a declarative, particle-centric interface, while the framework handles data layout and scalar or vector execution outside the kernel. The same kernel source is instantiated at compile time for user-defined layouts, including AoS, SoA, and AoSoA, and for scalar or explicitly vectorized CPU execution. We additionally show how the abstraction integrates with a conflict-free shared-memory traversal. Microbenchmark results show low abstraction overhead for the evaluated direct-sum kernels: scalar configurations remain within 4% of comparable handwritten references, while SIMD configurations achieve performance parity with explicitly vectorized handwritten kernels. Controlled comparative benchmarking against LAMMPS demonstrates competitive shared-memory CPU performance relative to the evaluated single-rank OpenMP configuration. These results show that C++ compile-time programming mechanisms enable particle simulations to retain modularity and flexibility with minimal abstraction cost.

Diff-GNN: Differentiable Graph Neural Networks for Joint Hardware-Software Partitioning and Scheduling
Siddhartha Shankar Das (PNNL), Zakaria Mehrab (Univ. of Virginia), James Kotary, Rounak Meyur, S. M. Ferdous, Erdal Mutlu, and Mahantesh Halappanavar (PNNL)

Hardware/software (HW/SW) partitioning is a fundamental problem in embedded system co-design, where each task must be assigned to either hardware or software under area constraints to minimize end-to-end execution time, also known as makespan. In the single-software, multiple-hardware setting, the problem is tightly coupled with scheduling because communication and software-task ordering directly affect the makespan. Existing approaches, including mixed-integer linear programming and metaheuristics, often scale poorly, whereas learning-based methods often do not jointly optimize task placement and ordering due to the non-differentiable nature of the scheduling process. We propose Diff-GNN, a differentiable Graph Neural Network (GNN) framework for joint HW/SW partitioning and scheduling. Diff-GNN uses a GNN encoder to jointly predict soft HW/SW assignments and SW-task priorities, and optimizes them with a differentiable scheduler that approximates makespan under precedence, communication, and software-serialization constraints. The model is optimized directly on each input task graph in a transductive, self-supervised manner, eliminating the need for a separate corpus of solved training graphs. At inference time, solutions from the placement head are discretized, repaired to satisfy hardware area constraints, and refined to improve solution quality. Experiments on 7 real benchmark task graphs show that Diff-GNN achieves the best overall performance among the classical, metaheuristic, and learning-based feasible baselines. These results highlight differentiable joint placement-and-order learning as a practical, scalable approach to HW/SW partitioning.

Keynote Talk: Intelligence Where the Task Is

Daniela Rus (MIT)

Parametrized Exact Hardware-Software Partitioning
Cameron Ibrahim, S.M. Ferdous, Erdal Mutlu (PNNL), Ilya Safro (Univ. of Delaware) and Mahantesh Halappanavar (PNNL)

When optimizing computing architecture for specific computationally intensive tasks, such as evaluating or training a neural network, it is important to identify what computational subtasks will offer the greatest decrease in cost (e.g., wall clock time or energy usage). This problem is known as Hardware-Software (HS) Partitioning, and it has a variety of formulations, many of which are NP-Hard. In this paper, we will define a family of HS Partitioning formulations which admit an exact fixed parameter tractable algorithm based on the directed pathwidth of the given task graph and show that this family of problems contains multiple existing formulations such as makespan minimization. Finally, we examine task graphs with small directed pathwidth that arise in real world applications and show that our algorithm can provide a speed up of up to 200x over a comparable linear programming approach utilizing the Gurobi ILP Library.

Joint Optimization of HW/SW Partitioning and Scheduling with Policy Gradient Methods

James Kotary (PNNL), Zakaria Mehrab (Univ. of Virginia), Siddhartha Shankar Das, Rounak Meyur, S. M. Ferdous, Erdal Mutlu, and Mahantesh Halappanavar (PNNL)

Hardware/Software (HWSW) Partitioning is a fundamental problem in embedded systems design, which calls for the optimal assignment of subtasks within a software program to either the CPU, or a dedicated hardware implementation. The problem is inherently tied to the subsequent optimal scheduling of tasks, which also determines the total runtime or makespan. The coupled problems are NP-Hard, and grow quickly with the size of the program, which challenges traditional combinatorial optimization methods. While many existing approaches optimize partitions over surrogate objectives to overcome the complexities of scheduling, they fail to optimize makespans directly. This paper proposes a differentiable framework for gradient-based optimization of the Joint HW/SW Partitioning and Scheduling Problems (JPSP), drawing on recent advancements in reinforcement learning for combinatorial problems. It presents a novel simulation framework that casts the problem’s solution space into a sequential decision-making problem that encapsulates both partitioning and scheduling. By forming the JPSP as a sequence of discrete decisions, we show that graph neural networks can be trained over the software task graph by Monte Carlo gradient estimation to optimize the alignment of the partition and schedule, yielding lower makespans when compared to a variety of strong baseline methods.

4-P1: Performance Engineering for AI; General Purpose GPU Computing Poster Session (12:15 PM-01:15 PM)

Session Chair/Session Host: K. Keville

CARP-RAG: Compute-Aware Adaptive Retrieval for Efficient Retrieval-Augmented Generation
Abhishek Kumar (Univ. of Cumberlands)

Retrieval-augmented generation (RAG) commonly uses a fixed retrieval depth even though evidence requirements vary across queries. This paper presents CARP-RAG, a compute-aware retrieval planning framework that treats retrieval depth as a controllable inference parameter. We evaluate two lightweight planner instantiations without retraining the retriever or generator: a rule-based latency-budget planner and a score-aware context-allocation gate. On a 500-query SQuAD workload, static k = 3 achieves the best F1 (0.5720), while increasing k to 5–20 does not improve answer quality. Under a 0.040-s budget, the rule-based CARP planner selects an average depth of 4.292 and achieves F1 = 0.5645, compared with F1 = 0.5624 for static k = 5. To test whether adaptation is useful on heterogeneous evidence requirements, we additionally evaluate a frozen score-aware planner on 500 held-out HotpotQA queries after calibration on a disjoint 500-query development split. Relative to static k = 10, Score-CARP reduces propagated passages by 11.34% (average k = 8.866) while supporting-document recall changes from 0.822 to 0.805 and complete-support retrieval from 0.672 to 0.640. Paired bootstrap 95% confidence intervals for these differences are [−0.026, −0.009] and [−0.048, −0.018], respectively. The results show that adaptive retrieval exposes a measurable quality–compute tradeoff and that retrieval demand varies substantially across multi-hop queries. 

Toward RL-Guided GPU Compiler Optimization:  Case Studies on Nvidia Blackwell GPUs

Xiteng Yao, Martin Herbordt (Boston Univ.)

Runtime rewards let reinforcement learning (RL) search for faster GPU kernels, but do not explain how an edit affects compilation or execution. We investigate what additional evidence helps interpret optimization attempts through three cases on NVIDIA GB200. We check outputs and compare paired runtimes, adding compiler fingerprints and no-change controls for selected experiments. First, we vary the workload and split factor of an attention kernel. Splitting creates more parallel work but adds a step to combine partial results. It helps launches with few thread blocks, while aggressive splitting slows a separate short-sequence configuration with more initial blocks.  Second, we compare compiler transformations on a fixed gather kernel that reads selected array elements. Forty-eight pass sequences in Triton GPU intermediate representation (TTGIR) form two TTGIR fingerprint classes. These remain distinct through LLVM IR but converge to the baseline class of normalized native GPU instructions (SASS). Matching fingerprints do not establish executable identity, and these recipes receive no separate timings under our grouping policy. Forced LLVM loop unrolling on the same gather changes normalized SASS and yields a 1.890–1.900× speedup over the baseline.  Third, we use RL sampling and restricted enumeration to test SASS edits after compilation. On three dense matrix multiplication (GEMM) configurations that leave most GPU multi processors idle, we move an existing asynchronous copy from global to shared memory earlier and clear operand-reuse hints.  This combined edit gives 13.0–15.3% speedups. A separate FP8 mixture-of-experts (MoE) probe clears reuse hints on arithmetic instructions and yields near-baseline timings despite changing native code. These cases connect observed outcomes to different follow-up experiments. Testing this evidence as additional RL feedback remains future work.

GPU-Based Parallelization of Differential Evolution Variants: Application to Solving Large Systems of Nonlinear Equations
Diogo Martins, Bruno Silva, Luiz Guerreiro Lopes (Univ. of Madeira)

Differential Evolution (DE) is a well-established evolutionary algorithm widely used for global optimization over continuous search spaces. However, it can become computationally demanding when applied to large-scale optimization problems. Modern GPUs offer massive parallelism, high memory bandwidth, and high floating-point throughput, making them well-suited to accelerating population-based algorithms. This paper presents GPU-accelerated implementations of the standard DE algorithm and three well-known variants: SHADE, jDE, and CoDE. Their computational performance and scalability are evaluated using ten large-scale systems of nonlinear equations, reformulated as nonlinear optimization problems, with dimensionalities ranging from 500 to 2,000 variables. Execution times obtained on the NVIDIA A100 and V100S GPUs are compared with those of the corresponding sequential implementation running on an AMD EPYC 7643 CPU. The results show substantial reductions in execution time for all four algorithms and across all tested problem dimensions, with mean speedups reaching approximately 69× on the A100 and 42× on the V100S. The A100 also exhibits better scalability at the largest problem dimensions.

Performance Engineering of Retrieval Architectures for Enterprise Supply-Chain Question Answering
Alex Carroll, Elenna Dugundji (MIT)

Enterprise question answering often selects evidence from heterogeneous documents, relational tables, event records, and supply-chain graphs before generating an answer. This source-selection stage creates a systems trade-off: local retrieval is inexpensive, while task-aware agentic routing can invoke additional reasoning, tools, and verification. We present a common harness and an 80-query, six-source workload for comparing TF-IDF lexical retrieval, deterministic GraphRAG-light, fixed lexical–graph fusion, retrieval-result caching, and a live agentic source router. We measure exact source-set accuracy, set F1, multi-source recall, abstention, latency, call counts, stability, and failure modes. The agentic router achieved 82.50% exact source-set accuracy and 86.84% set F1, compared with 38.75% and 61.00% for TF-IDF. GraphRAG-light did not improve the lexical baseline; fixed fusion increased exact accuracy to 41.25%. Agentic execution had 6.67 s mean and 9.88 s P95 latency, whereas local retrieval operated at millisecond scale. Fully warm cache hits preserved hybrid predictions and reduced repeated-result lookup to approximately 0.015 ms. The results quantify an accuracy–latency envelope without claiming functional equivalence between retrieval-only, cached, and live end-to-end execution. 

4-2: Mapping and Scheduling of Parallel and Real-Time Applications (12:30 PM-01:45 PM)

Session Chair/Session Host: X. Sun & J.Ghanem

Invited Talk: Compiler 2.0: Compilers in the Era of Machine Learning

Saman Amarasinghe (MIT)

Bounding Both Ends of an Anticipatory FPGA Scheduler
Syed Daniyal Naqvi (University of Liverpool)

Predictive gating in dual-path FPGA systems, a lightweight model kept always on and a heavyweight model switched on only when required, is typically an unbounded engineering heuristic: no guaranteed lead time for switching safely, and no bound on how long the predictor may remain unreliable before that is detected. A 2026 systematic review of 36 FPGA-based safety-critical AI accelerator studies found that no system provided worst-case execution time (WCET)-style timing guarantees [24]. We turn this heuristic into a bounded hardware primitive: a 4-state scheduling finite-state machine (FSM), implemented in explicit register-transfer level (RTL), gating a heavyweight hls4ml inference path through BUFGCE (Xilinx’s clock-buffer primitive for glitch-free clock enable/disable), with two independently derived bounds. kmin, the minimum lead time before switching paths, comes from measured HLS pipeline depth, with its conservative implementation margin confirmed against RTL simulation to within one cycle. kmax, the maximum duration the system may remain unstable under sustained predictor thrash, is enforced by FALLBACK, an RTL, cycle-exact instantiation of the Simplex fail-safe pattern [20] reverting the system to a statically safe configuration. The design closes timing at 125MHz with zero failing endpoints across 80,369 endpoints, at under 9% resource overhead. Stress-tested against real 2023 Formula 1 telemetry across three circuits, Path B’s clock-enable duty cycle falls from 100% (static) to 53–76% depending on circuit geometry, cross-validated to within 1.5 percentage points, with no per-circuit retuning. FALLBACK is functional under forced-thrash injection and, checked against the same telemetry, never triggered organically. A software equivalent of the decision logic, benchmarked on real hardware, is 19× slower than the hardware kmin budget at the median and up to four orders of magnitude slower in the observed tail. The scheduling interface is designed to generalise to any clock-enable-pin (CE-pin)/BUFGCE-gated dual-path FPGA classifier.

SSTA-Trace: LLM-Learned Scheduling of Statistical Static Timing Graphs on GPU
Chedi Morchdi (Texas A&M Univ.), Cheng-Hsiang Chiu (Univ. of Wisconsin), Yi Zhou (Texas A&M Univ.), Tsung-Wei Huang (Univ. of Wisconsin)

Statistical Static Timing Analysis (SSTA) models circuit delays under process variations by propagating random variables through timing graphs using statistical sum and max operations. The resulting computation forms a task graph consisting of thousands of GPU tasks. However, existing GPU task graph schedulers are limited to general-purpose heuristics, such as greedy dispatching, that do not account for the characteristics of SSTA workloads. To overcome this challenge, we present SSTA-Trace, a large language model (LLM)-based framework for scheduling SSTA task graphs on GPU. Our approach leverages Trace, an LLM-driven program optimization framework, to automatically learn scheduling policies by directly optimizing executable policy code using structured feedback. The learned policies incorporate both local features and global graph information, including critical-path metrics. We evaluate our approach on seven large SSTA circuit graphs. Experimental results show that the learned policies consistently outperform a greedy lowest-workload baseline and a HEFT-style DAG scheduling baseline, achieving up to 23.7% runtime reduction.

HLS4LFADS: A Framework for Real-Time and Parallel Neural Decoding on FPGAs
Chi-Jui Chen (National Yang-Ming Chiao Tung Univ.), Yan-Lun Huang (Univ. of Texas Austin), Xiao-Han Liu, Atharva Mattam, Hao Fang (Univ. of Washington), Ling-Chi Yang, Chia-En Chang (National Yang-Ming Chiao Tung Univ.), Elham E. Khoda, Eli Shlizerman, Amy L. Orsborn, Scott Hauck, Shih-Chieh Hsu (Univ. of Washington), and Bo-Cheng Lai (National Yang-Ming Chiao Tung Univ.)

Latent Factor Analysis via Dynamical Systems (LFADS) is widely used to infer low-dimensional latent dynamics from population neural recordings and has been applied across neural decoding tasks. Closed-loop systems require decoding to complete within each temporal bin. CPUs and GPUs can meet this deadline for moderate workloads, but longer input sequences or multiple concurrent models increase latency. Field-programmable gate arrays (FPGAs) offer model-specific parallelism and spatial replication, yet limited resources and model-specific implementation effort hinder deployment. We present HLS4LFADS, an end-to-end FPGA framework that combines layer-wise calibrated fixed-point quantization with quantization-aware training, extends hls4ml to automatically generate accelerators for the complete LFADS inference graph, and supports concurrent inference through multi-compute-unit (multi-CU) deployment. On a Xilinx Alveo U55C, three concurrent CUs achieve mean end-to-end latencies of 0.367 ms and 0.696 ms for the monkey-reaching and synthetic Lorenz tasks, respectively. These values represent increases of only 11.2% and 6.9% over the corresponding single-CU latencies and remain below their respective 10 ms and 6 ms bin intervals. 

Agentic CRAMP: Runtime-Adaptive Scheduling for Scalable Parallelism of Classifiers and Regressors on Distributed and Multicore Systems
Baidya Nath Saha, Wali Mohammad Abdullah, Md. Morshedul Islam (Concordia Univ. of Edmonton)

CRAMP [1] introduced a static taxonomy that maps classifiers and regressors onto four parallelization paradigms – MapReduce, multicore, multithreading, and gradient-based optimization – reporting, per algorithm, a single serial-to-parallel speedup under a fixed, upfront work partition. This paper asks the complementary question CRAMP leaves open: within a given paradigm, does replacing CRAMP’s static partition with a runtime-adaptive, agentic scheduler that observes worker telemetry and dynamically rebalances work through a shared queue yield further, predictable gains, or does CRAMP’s algorithmto-paradigm mapping already capture most of the achievable benefit? We answer this with a concrete five-role controller – environment, controller, memory/telemetry, tool layer, and guardrails – that watches workers, decides how to split remaining work, moves that work, and checks the result before acceptance. We formalize the agentic scheduling problem, prove a tight Ω(w · maxu tu) idle-time bound for static partitioning under heterogeneous per-unit costs, and prove that agentic scheduling preserves the exact numerical output of every algorithm (no accuracy trade-off, unlike CRAMP’s accuracy-speedup metric). We benchmark six CRAMP-relevant algorithms (SVM, KMeans, PCA, Fisher Discriminant Analysis, AdaBoost, Bayesian Networks) across CRAMP’s four paradigms and five datasets – a synthetic heterogeneous-cost benchmark plus California Housing, MNIST, 20 Newsgroups, and Speech Audio – yielding 240 measurements, each verified against a serial reference to within 10−7-10−8 numerical equivalence. Agentic scheduling wins over CRAMP-style static partitioning in 50.8% of the 120 algorithmparadigm-dataset configurations, with gains up to +82.6% (AdaBoost, gradient-descent, synthetic data) and losses up to −40.1% (PCA, gradient-descent, California Housing). These results show CRAMP’s static taxonomy is a strong but incomplete predictor of achievable parallel performance: paradigm granularity and dataset-specific cost heterogeneity interact with the scheduling policy in ways an algorithm-only taxonomy cannot capture, motivating a runtime-adaptive refinement of CRAMP’s guidance together with an explicit reproducibility audit of what was measured, re-executed, and left open.

4-P2: Advanced Multicore Software Technologies; Automated Design Tools; Mapping and Scheduling of Parallel and Real-Time Applications Poster Session (01:45 PM-02:45 PM)

Session Chair/Session Host: K. Keville

Linux Support for CPU Stress Test on Large-Scale AMD EPYC Systems
S. Biplab Raut (AMD)

The AOCL CPU Stress Test (CST) validates processor stability under sustained computational and memory pressure using AMD’s optimized BLIS and LibFLAME numerical libraries. Originally developed for Windows desktop environments with a 64-core limit, CST failed critically when deployed on high core count AMD server-class CPU platforms, such as a dualsocket EPYCTM 9654 system with 192 physical cores and 1.5 TB DDR5: CPU stress achieved only 2% utilization, memory setup timed out, and blend mode produced 0% CPU activity. This paper presents four engineering solutions that enable CST on Linux at server scale: a POSIXR threading and synchronization layer, mmap-based parallel memory allocation with transparent huge pages, an L3-cache-topology-aware two-level OpenMP threading model, and a restructured synchronization protocol for blend mode. The resulting system achieves 99% CPU utilization across all 192 cores, 1,403 GB (95%) memory residency with setup in approximately 5 seconds, and simultaneous CPU-plus-memory stress – all with clean cooperative shutdown within 60 seconds. 

Intent-Preserving FPGA-SoC Integration Using a Design-Time Metadata Intermediate Representation
Lewis McLaughlin, Louise H. Crockett, Robert W. Stewart (Univ. of Strathclyde)

FPGA system-on-chip design commonly involves composing packaged intellectual property (IP) and exposing the resulting hardware to runtime software. Across this workflow, integration information such as numeric datatype, sample rate, framing, and connection purpose can be reduced to widths, parameters, or software constants, obscuring the intent from which the system was constructed. We present PRISM, a prototype that uses and extends the PYNQ-Metadata object model as a design-time intermediate representation. PRISM imports AMD IP descriptions, retains integration intent, and relies on Vivado for vendor-specific configuration, allowing block-design Tcl and runtime metadata to be derived from one resolved graph. The evaluation includes all 605 components in the installed Vivado 2025.2 library, each of which parsed successfully. A PYNQ-Z2 FIFO loopback demonstrates that the evaluated datatype, rate, framing, connection, clock, and address information remains explicit in the resolved graph and runtime metadata and changes consistently with authored inputs; its generated bitstream transported 1,024 words with exact equality. Four larger RFSoC scopes reached stable design state and passed Vivado block-design validation. Together, these results support the extended object model as a persistent design-time representation for the evaluated structural categories and integration properties.

Satoorn: A Source-to-Source Conversion Tool for Safety Critical Model Based Generated GPU Code
Marcos Rodriguez, Alejandro J. Calderón (Ikerlan Research Center), Leonidas Kosmidis (Barcelona Supercomputing Ctr.), Irune Yarza (Ikerlan Research Center)

Model-Based Design (MBD) and safety-critical standards intersect in many ways that can enhance the product development process. Safety-critical systems require rigorous methodologies to ensure reliability, while MBD leverages mathematical models to optimise system development and reduce human errors. Traditionally, these fields have been applied to CPU-based architectures, with extensive literature documenting their success. However, the introduction of Graphics Processing Units (GPUs) in heterogeneous computing presents new challenges for safety compliance. These challenges arise, among others, from the parallel nature of GPUs; their complex memory management, which complicates the prediction of program execution times; and the use of commonly used programming languages that introduce memory vulnerabilities through pointers and dynamic memory allocation. In this work, we present Satoorn, a tool that bridges the gap between MBD-generated code and safety-compliant languages for GPUs. Satoorn transforms Simulink-generated CUDA code into Brook Auto, a safety-critical-compliant GPU language according to ISO 26262. This tool enhances the integration of MBD artefacts into safety-critical systems, ensuring adherence to stringent safety standards. We evaluate this approach using CUDA code generated from a Simulink model for a lane-tracking example representing part of an image-processing pipeline for automotive sensors.

GRAPHSCHED: Heterogeneous Graph-Augmented Multi-Objective Reinforcement Learning for Energy-Aware HPC Workload Scheduling
Kyrian Adimora, Hongyang Sun (Univ. of Kansas)

Modern high-performance computing (HPC) facilities face mounting pressure to simultaneously maximize throughput, resource utilization, and energy efficiency while adapting to heterogeneous and dynamic workloads. We present GRAPHSCHED, a multi-objective scheduling framework that integrates heterogeneous graph neural networks (GNNs) with Proximal Policy Optimization (PPO) and Monte Carlo Dropout uncertainty quantification (UQ). Unlike prior work, GRAPHSCHED encodes only features directly available in production job logs: submit time, requested walltime, node count, CPU-core count, queue wait time, and per-node RAS failure counts, ensuring full reproducibility on public ALCF trace catalogs. A dual-attention message-passing encoder captures local job-resource compatibility and global cluster utilization patterns, while a three-component reward jointly optimizes bounded slowdown, utilization, and an idle/peak CPU-power proxy that we empirically probe against real ALCF GEOPM hardware traces. We evaluate 389,620 production jobs from four ALCF systems (Polaris, Aurora, Theta, and Mira) using strict chronological splits and report all results as mean± and 95% confidence intervals across five independent seeds. GRAPHSCHED achieves 29.1% lower average bounded slowdown, 31.7% higher CPU utilization, and 16.8% lower estimated CPU energy versus EASY-backfilling and outperforms the strongest DRL baseline (DRAS [1]) by 7.1% in slowdown and 9.4% in utilization. We further report a fully transparent, leakage-safe (node-grouped) validation of the on-node power model against GEOPM hardware measurements, discussing where the model’s explanatory power is limited.

LockRoute: A Spatial Locking Framework for Parallel Global Routing
Amber Thrall (Washington State University), Vidya Chhabria (Arizona State Univ.), S M Ferdous, Mahantesh Halappanavar (PNNL), Bala Krishnamoorthy (Washington State University)

Global routing is a crucial step in VLSI design that has become increasingly more complex as chip sizes and design scales grow. Many global routers divide the process into several stages: two-pin decomposition, congestion map generation, maze routing and layer assignment. Each of these stages requires routing thousands to millions of nets providing opportunities for parallelization. In this paper, we demonstrate that global routing is not embarrassingly parallel and describe a lock-based approach to shared-memory parallel global routing by identifying net dependencies through the use of an R-tree. This lock framework is flexible enough to be applied to every stage of the global routing pipeline. We evaluate our global router on the ISPD 2008 and ISPD 2019 global routing contest benchmark suites. Our approach achieves 3.45×–11.35× speedup in runtime compared to other routers without a reduction in quality.

ML Based Modeling of XSEDE/ACCESS Usage and Performance data for HPC Job Wait Time Estimates and Resource Allocation
Abani Patra, Bipin Gaikwad (Tufts Univ.), Nikolay Simakov, Joseph White, Thomas Furlani (Univ. of Buffalo)

Our research goal is effective data-driven resource allocation, deployment and usage strategies for HPC to meet multiple stakeholder goals. We identify the following primary stakeholders: a) users, b) resource owners, and c) resource managers. Users want to minimize job throughput with minimal queue wait times while resource owners wish to minimize total cost – capital and operations. Resource managers have to balance both users’ and resource owners’ interests! The recent workload transformation with AI workloads stretching HPC resources makes optimal resource usage necessary. Analytics support for making these complex decisions is therefore critical. The complex mix of user demand (job types, temporal fluctuations) and resource dynamicity and complexity makes this a challenging problem. Quality of Service (QoS) measures can include job queue wait time. In the case of resource managers, operations and investment choice policy decisions are critical.

Breaking the Interconnect Bottleneck in LLM Serving via Congestion-Aware Scheduling over Heterogeneous Interconnects
Dong Liu (UCLA), Yanxuan Yu (Columbia Univ.), Chang Liu (Univ. of Illinois Urbana-Champaign), Eric Jiang (UCLA), Tony Geng (Rice Univ.), Ying Nian Wu (UCLA)

Modern LLM serving clusters expose a stratified fabric of interconnects—NVLink, PCIe, host-memory staging, and InfiniBand/RoCE—that differ not only in bandwidth and latency, but also in reachability, transfer semantics, and shared-resource coupling. Production frameworks nevertheless bind transfers with launch-time, class- and load-oblivious policies, treating these fabrics as interchangeable wires. We instrument a 64-GPU cluster and find that 71% of tail TTFT requests (those at or above the empirical P99) coincide with interconnect congestion while an admissible alternative decision—another RDMA rail, an equivalent decode replica, or host staging—remains underutilized (median residual-capacity ratio 2.4×; mean 3.1×). We present HICS (Heterogeneous Interconnect Congestion-aware Scheduler), a runtime layer that jointly selects fabric, transport mode, placement, and path for slack-tolerant KV transfers and request placement, while coordinating with preconfigured NCCL communicators for latency-critical TP/PP traffic. HICS integrates with vLLM/SGLang via a thin shim (0.73 μs scheduling latency and <2 μs including chunk dispatch). On Llama-3-70B and Mixtral-8×7B under realistic traces, it reduces P99 TTFT by 41% and raises sustained output-token throughput by 28% over the best static baseline—gains that shrink under homogeneous multipath alone. Code: https://github.com/FastLM/CongShed.

TriShield: A Unified ASIC Architecture for Composable TEE, FHE, and Differential Privacy with Leakage-Aware Formal Guarantees
Akram Sheriff (Carnegie Mellon Univ.)

Software composition of trusted execution environments (TEEs), fully homomorphic encryption (FHE), and differential privacy (DP) leaves seams where side channels andunattested noise break end-to-end privacy. TriShield co-locates TEE cryptography, Cheon–Kim–Kim–Song (CKKS) FHE, and DP sampling on one residue-number-system (RNS) datapath with a silicon privacy ledger that refuses release when the DP budget (ε, δ) or calibrated leakage L would be exceeded. We contribute: (i) leakage→R´enyi DP (RDP) under explicit assumptions with surcharge ρL = max{ρchain, ρFish}; (ii) encrypted-noise DP (EDDP) under the same CKKS public key as the payload, with measured CKKS decoding-error sensitivity inflation; (iii) a mutualinformation (MI) estimator beyond Test Vector Leakage Assessment (TVLA), with held-out seed validation; (iv) cycle-accurate exclusive-mode field-programmable gate array (FPGA) evidence; (v) a measured end-to-end ED-DP demo. On a Xilinx Alveo U280 FPGA (14,247 lines of SystemVerilog at 127 MHz), ResNet-18 on CIFAR-10 reaches 93.0%}0.3% at 512 ms and 0.14 J per query with L ≤ 0.008 bits/query under our probe model. Applicationspecific integrated circuit (ASIC) area amortization (4.2–8.7×) is labeled Projected. We position against CROSS, Taiyi, DNA-HHE, and Confidential Federated Computations (CFC), and separate proved, measured, and conjectural claims. An evidence-maturity table states exactly what remains for a top-systems/security lock (ASIC P&R, multi-board (G4), UC).

4-3: Performance Engineering for AI (02:15 PM-03:30 PM)

Session Chair/Session Host: N. Zhang & P. Luszczek

BASP: Communication-Efficient Batch-Aware Sequence Parallelism for LLM Training
Bigyan Ghimire, Jon Calhoun (Clemson Univ.)

Long-context reasoning for large language models (LLMs) is becoming increasingly important, but training over long sequences remains challenging due to massive memory and communication requirements. Sequence parallelism has emerged as an essential technique for addressing bottlenecks in long-sequence LLM training. However, we observe that existing sequence-parallelism methods are batch-agnostic and apply uniform sequence partitioning across all batch sizes, resulting in inefficient communication. In this paper, we introduce Batch-Aware Sequence Parallelism (BASP), a sequence-parallelism approach that leverages batch structure to reduce communication overhead. BASP exploits batch structure by partitioning GPUs into disjoint sequence-parallel groups according to the micro-batch size. This design reduces the all-to-all communication group size, thereby localizing communication and improving training efficiency. Experimental results on an NVIDIA A100 cluster show that BASP improves end-to-end training time by 1.17–1.31× in Llama and Qwen models compared to standard sequence-parallel baselines, while preserving identical model accuracy and memory usage.

To CHAI or Not To CHAI: Chapel+AI for Training and Inference
Mohamed Abdelnaby, Paul Sathre, Wu-chun Feng (Virginia Tech)

While deep learning (DL) is being increasingly used in high-performance computing (HPC), the compiled ecosystems of HPC lack native support to train neural networks, leaving modern artificial intelligence (AI) confined to Python frameworks, where a high-level front-end issues and dispatches the kernels that a C++/GPU runtime executes. To address this gap, we present CHAI 1.0, a compiled Chapel interface that brings
artificial intelligence into a parallel HPC language by binding to the same LibTorch 2.6.0 runtime that PyTorch uses. Across 22 DL models on NVIDIA A100 and H200 GPUs, we evaluate four DL training configurations: CHAI (eager), CHAI Graphs, PyTorch (eager), and PyTorch Graphs. The performance of our ChAI 1.0 matches or surpasses that of PyTorch (eager) on every DL model while it matches that of PyTorch Graphs on recurrent neural networks (RNNs) and transformer models but lags on convolutional neural networks (CNNs) due to two optimizations that CHAI lacks: (1) Inductor operator fusion and (2) the Channels Last memory layout.

Selector–Solver Coordination in Vision Language Model-Guided Combinatorial Optimization
Yadu Shaji Nair, Elenna Dugundji (MIT)

Hybrid systems that pair a learned selector (e.g., an ML model, LLM, or VLM) with a classical operations-research (OR) solver are becoming widely adopted to solve large-scale combinatorial optimization problems. Such systems are typically orchestrated using a static FIFO queue and are evaluated only by using the final solution quality and solver speed. This evaluation methodology is lacking because it fails to account for a fundamental systemic property: the learned model not only generates high-quality candidates for the OR solver, but also produces the workload that will be processed by that OR solver. Using the ViTSP framework as an experimental platform, we recast vision-language-model (VLM)-guided traveling-salesman solving as a selector–solver measurement problem. A rate model connecting candidate supply, solver capacity, and acceptance, validated on a 240-run grid, shows that useful progress is not raised by parallelism alone and that the binding bottleneck shifts with the size of the instance. A controlled selector-delay experiment supports the bottleneck law X ≈ min(λ, μ) as a regime-level predictor, with correlation r = 0.77 between predicted and measured throughput, rather than as an exact per-setting predictor. Guided by this model, we introduce value-aware, pressure-gated orchestration for candidate prioritization based on expected accepted improvement per solver second (analogous to a cμ-rule index) and admit candidates as long as normalized solver pressure remains bounded. On a 45-run audited final grid over five TSPLIB instances, the proposed family obtains a lower mean final tour-length objective than FIFO on four of five instances under queue pressure. The fixed pressure-gated variant is most robust, the adaptive AP-VAO extension is best in the balanced regime, and the one FIFO win shows that pressure control must preserve exploration. We claim regime-dependent improvements, not universal laws or statistical significance from the small final grid.

Software-Customized LLM Serving on Large-HBM GPUs
Zhihui Du, Diptorup Deb, Clint Greene, Yao Liu, Rishi Madduri, Mukhil Azhagan Mallaiyan Sathiaseelan, Debasis Mandal, Phani Vaddadi, Viswanath Vadlamani, Anuya Welling (AMD)

Long-context LLM inference exposes a backend-selection problem: as prompt lengths grow, the optimal prefill execution path changes across workload regimes, and no single static path dominates. Hardware disaggregation—dedicating specialized accelerators to each inference phase—addresses this at the infrastructure level but requires significant capital investment. This paper proposes a software-customization approach for unified large High-Bandwidth Memory (HBM) GPUs that solves the same problem through three coordinated steps: (1) building highly optimized architecture-specific prefill paths that exploit matrix multiply-accumulate (MMA) hardware to close the gap between generic and architecture-optimized attention at long context; (2) designing a multi-path stack that supports all workload types—long, short, regular, and ragged—on shared hardware; and (3) identifying a transition band—a context-length region where the two paths perform similarly (gap 0.5–20%)—so that placing the scheduling threshold at the band midpoint bounds worst-case suboptimality to the small within-band gap, rather than the large out-of-band gap (17–88%) that a misplaced hard threshold would incur. Per-node calibration is necessary: the band location varies between hardware instances of the same GPU model and cannot be assumed constant across a cluster, but a short offline sweep resolves this before serving begins. This framework is instantiated on AMD Instinct MI300X, validated with microbenchmarks and end-to-end LLM serving across two internal large-HBM GPU clusters (99 s startup, ≤1.24 s warm latency). Split-fallback at 512K context achieves 5.91–5.95× speedup over the default path, establishing a hard OOM boundary at 1M context on a single MI300X. The resulting scheduler matches the best available path in 55 of 60 holdout cases, with median latency only 0.0263% above the oracle optimum.

4-P3: Graphs Poster Session (03:30 PM-04:30 PM)

Session Chair/Session Host: M. Pelletier

Traffic Matrices for Anonymized High Performance Analysis of Physical/Data/Network/Transport/ Session/Presentation/Application Layers
Martin Satterfield, Justin Wynn, Grant Blakely, Tyler House, DJ Hovermale (UAH), Hayden Jananthan, Jeremy Kepner (MIT)
In all domains protection requires observing the domain and analyzing the observations. Effective cyber domain observation and analysis must be done with the highest regard for privacy. In the broader networking community anonymized source-to-destination traffic matrices with standard data sharing agreements have emerged as one approach to meeting many of these requirements. Traffic matrices are highly adaptable and sources/destinations can be any combination of physical, logical, persona, and/or AI agent endpoints. This work illustrates traffic matrix flexibility by applying the traffic matrix concept to various layers in the standard OSI Model. An easy-to-understand Python example code has been developed that creates and stores network traffic in these various layers to binary (GraphBLAS) and text (D4M) formats. The rates and compressions of the example code are presented demonstrating significant compression and the ability to handle Gigabit/s scale networks with modest computing resources. 

Clique Search in Simultaneously Partitioned Graphs
Peter Schmidt, Sandor Szabo, Bogdan Zavalnij (Renyi Institute)

Many important applied combinatorial optimization problems can be reduced to locating a k-clique in a graph and, consequently, can be handled by a clique solver. In the particular case where the nodes of the graph are properly colored with k colors—that is, when dealing with a k-partite graph—the clique-search algorithm can be sped up. In this paper, we point out that there are naturally occurring combinatorial optimization problems that can be reduced to k-clique problems, but the underlying graph admits more than one k-partitioning. We refer to such a graph as a simultaneously k-partitioned graph or a b-fold k-partite graph. The presence of additional k-partitions of the nodes can improve the efficiency of the clique solver. In addition, the k-partitions play a role in the preconditioning phase of the problems.

4-4: Fastcode (03:45 PM-05:30 PM)

Organizers: B. Hoppe & T. Kaler

Invited Talk: Beyond Correct — Teaching AI to Actually Solve Hard Problems

Alvin Cheung (Berkeley)

Invited Talk: The Post-Developer Era

Tim Kraska (MIT)

Invited Talk: LLMs Are Great at Code Generation, But What About Code Adaptation?

Justin “Goju” Gottschlich (Merly)

Invited Talk: Green Means Stop — Building the Reward Signal Code Optimization Never Had

Jatin Ganhotra (IBM)

4-5: GenAI Opportunities & AI Challenges (05:30 PM-07:30 PM)

Organizers: D. Burrill & V. Gadepally & C. Prothman

Invited Talk: Intel Crescent Island

Hong Jiang (Intel)

Invited Talk: Rearchitecting the Datacenter Lifecycle for AI

Chaojie Zhang (Microsoft)

Invited Talk: Language Model Architecture

Roger Waleffe (Nvidia)

Invited Talk: Powering AI: Energy, Control and Consequences

Shashank Yellapantula (NLR)