27th Annual
IEEE High Performance Extreme Computing Virtual Conference
25 - 29 September 2023

HPEC 2023 PROCEEDINGS

Friday, September 29

5-K: Keynote Session (10:30-11:00)

Co-Chairs: J. Kepner & A. Reuther

Speeding Progress, Advice for Research Managers
Dr. Ivan Sutherland (von Neumann Medal & ACM A.M. Turing Award Winner)

5-1: Quantum & Advanced Processor Architectures Session (11:00-12:15)

Co-Chairs: C. Byun & D. Ricke

Lincoln AI Computing Survey (LAICS)
Albert Reuther, Peter Michaleas, Michael Jones, Vijay Gadepally, Siddharth Samsi, Jeremy Kepner (MIT Lincoln Laboratory)
Accelerating Garbled Circuits in the Open Cloud Testbed with Multiple Network-Attached FPGAs
Kai Huang (Google), Mehmet Gungor, Suranga Handagala, Stratis Ioannidis, Miriam Leeser (Northeastern Univ.)
UNet Performance with Wafer Scale Engine (Optimization Case Study)
Vyacheslav Romanov (NETL)
Hybrid Quantum-Classical Multilevel Approach for Maximum Cuts on Graphs
Anthony Angone (Univ. of Delaware), Xiaoyuan Liu (Fujitsu Research), Ruslan Shaydulin (JPMorgan Chase), Ilya Safro (Univ. of Delaware)
Optimization and Performance Analysis of Shor’s Algorithm in Qiskit
Dewang Sun, Naifeng Zhang, Franz Franchetti (Carnegie Mellon Univ.)

Poster Session: 5-P (12:15-14:15) Poster Session

Chair(s)/Host(s): D. Enright & TBD

FFTX-IRIS: A Dynamic Execution System for Heterogeneous Platforms
Sanil Rao, Het Mankad (Carnegie Mellon Univ.), Mohammad Alaul Haque Monil (ORNL), Het Mankad (Carnegie Mellon Univ.), Jeffrey Vetter (ORNL), Franz Franchetti (Carnegie Mellon Univ.)
EVPFFTX: A First Look at FFTX Applications in Material Science
Het Mankad (Carnegie Mellon Univ.), Andrea Rovinelli, Miroslav Zecevic (LANL), Peter McCorquodale (LBNL), Franz Franchetti, Naifeng Zhang, Sanil Rao (Carnegie Mellon Univ.), R. A. Lebensohn, Laurent Capolungo (LANL)
SRAM Performance Tuning Via Flex-Gate Biasing
Elijah E Racz, Maher Rizkalla (Indiana Univ.-Purdue Univ. Indianapolis), Trond Ytterdal (NTNU), John Lee (Indiana Univ.-Purdue Univ. Indianapolis)
The Use of Differential Equations to Model Multiprocessors Architecture
Ricardo Citro, Kayla Zantello (Grand Canyon Univ.)
A Comparison of the Performance of the Molecular Dynamics Simulation Package GROMACS Implemented in the SYCL and CUDA Programming Models
Leonard Apanasevich, Yogesh Kale, Himanshu Sharma, Ana Marija Sokovic (Univ. of Illinois Chicago)
P2Prop: A Benchmarking Tool for Assessing Power to Performance Proportionality in HPC-grade GPUs
Ghazanfar Ali (Texas Tech Univ.)

5-2: ASIC/FPGA Advances & Design Tools 1 Session (12:30-13:45)

Co-Chairs: J. Hughes & B. Thoelen

Pruning Binarized Neural Networks Enables Low-Latency, Low-Power FPGA-Based Handwritten Digit Classification
Syamantak Payra (Stanford Univ.), Gabriel Loke, Yoel Fink, Joseph Steinmeyer (MIT)
Leveraging Mathworks Tools to Accelerate the Prototyping of Custom 5G Applications in Hardware
Joshua Geyster, Karen Gettings, Paul Monticciolo, Matthew Rebholz (MIT Lincoln Laboratory)
Generating High-Performance Number Theoretic Transform Implementations for Vector Architectures
Naifeng Zhang (Carnegie Mellon Univ.), Austin Ebel, Negar Neda (New York Univ.), Benedict Reynwar, Andrew G. Schmidt (USC Information Sciences Institute), Brandon Reagen (New York Univ.), Franz Franchetti (Carnegie Mellon Univ.)
Selective Encryption of Compressed Image Regions on the Edge with Reconfigurable Hardware
Justin Kawakami, Dominik Zajac, Miriam Leeser (Northeastern Univ.)
Quantifying the Gap Between Open-Source and Vendor FPGA Place and Route Tools
Shachi Vaman Khadilkar (UMass Lowell), Ahmed Sanaullah (Red Hat Research), Martin Margala (Univ. of Louisiana)

5-3: ASIC/FPGA Advances & Design Tools 2 Session (14:15-15:30)

Co-Chairs: J. Hughes & D. Ricke

Errant Beam Detection Using the AMD Versal ACAP and Vitis AI
Anthony M Cabrera, Yigit Yucesan, Frank Liu, Willem Blokland, Jeffrey S Vetter (ORNL)
Improved Models for Policy-Agent Learning of Compiler Directives in HLS
Robert P Munafo, Hafsah Shahzad (Boston Univ.), Ahmed Sanaullah, Sanjay Arora, Uli Drepper (Red Hat), Martin Herbordt (Boston Univ.)
Feature-Oriented FSMs for FPGAs
Justin Deters (SimpleRose), Peyton Gozon, Max Camp-Oberhauser, Ron K. Cytron (Washington Univ. St. Louis)
Towards a Flexible Hardware Implementation for Mixed-Radix Fourier Transforms
Mario Vega, Xiaokun Yang, John Shalf, Doru Thom Popovici (LBNL)
Tyche: A Compact and Configurable Accelerator for Scalable Probabilistic Computing on FPGA
Yashash Jain, Utsav Banerjee (IIS Bangalore)

5-4: Advanced Multicore Software Technologies 1 Session (15:45-17:00)

Co-Chairs: C. Byun & C. Long

Invited Talk: The Confluence of HPC, Data and AI for Science
Dr. Sudip Dosanjh (NERSC Director, LBL)
Finding Your Niche: An Evolutionary Approach to HPC Topologies [Best Paper Award]
Stephen J. Young, Joshua Suetterlein, Jesun Firoz, Joseph Manzano, Kevin Barker (PNNL)
IRIS-DMEM: Efficient Memory Management for Heterogeneous Computing [Outstanding Paper Award]
Narasinga Rao Miniskar, Mohammad Alaul Haque Monil, Pedro Valero-Lara, Frank Y. Liu, Jeffrey S. Vetter (ORNL)
The Aggressive Oversubscribing Scheduling for Interactive Jobs on a Supercomputing System
Shohei Minami, Toshio Endo, Akihiro Nomura (Tokyo Inst. of Tech.)
In-Place Multi-Core SIMD FFTs
Benoît Dupont de Dinechin (Kalray), Julien Hascoët (INSA Rennes, IETR / Kalray), Orégane Desrentes (INSA Lyon, CITI and Kalray)

5-S1: Advanced Multicore Software Technologies 2 Special (17:30-19:30)

Co-Chairs: D. Enright & S. Shankar

Multiarchitecture Hardware Acceleration of Hyperdimensional Computing
Ian Peitzsch, Mark Ciora, Alan George (Univ. of Pittsburgh)
Optimizing Compression Schemes for Parallel Sparse Tensor Algebra
Helen Xu (LBNL), Tao B. Schardl (MIT CSAIL), Michael Pellauer (NVIDIA), Joel Emer (MIT CSAIL)
ProtoX: A First Look
Het Mankad, Sanil Rao (Carnegie Mellon Univ.), Phillip Colella, Brian Van Straalen (LBNL), Franz Franchetti (Carnegie Mellon Univ.)
Dynamic Data Partitioning in the WAFL File System
Jian Hu, Matthew Curtis-Maury, Vinay Devadas (NetApp)
Accelerating Training Data Generation Using Optimal Parallelization and Thread Counts
Jonathan Levine, Leonard MacEachern (Carleton Univ.)